1 of 11 110706 features ? 3v or 5v operation ? ultra-low power consumption ? two digitally controlled, 256-position potentiometers ? 14-pin tssop (173 mil) and 16-pin so (150 mil) packaging available for surface-mount applications ? addressable using 3 address inputs ? 2-wire serial interface ? operating temperature range: - industrial: -40 c to +85 c ? standard resistance values: - ds1803-010 10k - ds1803-050 50k - ds1803-100 100k pin assignment pin description l0, l1 - low end of resistor h0, h1 - high end of resistor w0,w1 - wiper terminal of resistor v cc - 3v/5v power supply input a0, a1, a2 - chip select inputs sda - serial data i/o scl - serial clock input gnd - ground nc - no connection description the ds1803 addressable dual digital potentiometer feat ures two independently controlled 256-position potentiometers. device control is achieved through a 2- wire serial interface. thre e address pins allow up to 8 ds1803?s to share the same 2-wire interface. th e exact wiper position of each potentiometer can be written or read. the ds1803 is ava ilable in a 16-pin dip, 16-pin so , and 14-pin tssop package. the device is available in three standard resistance values: 10k ? , 50k ? , and 100k ? and is specified over the industrial temperature range. ds1803 addressable dual di gital potentiomete r www.maxim-ic.com h1 1 14 vcc l1 2 13 nc w1 3 12 h0 a2 4 11 l0 a1 5 10 w0 a0 6 9 sda gnd 7 8 scl ds1803 14-pin tssop (173 mil) h1 1 16 vcc nc 2 15 nc l1 3 14 h0 w1 4 13 l0 a2 5 12 w0 a1 6 11 nc a0 7 10 sda gnd 8 9 scl ds1803z 16-pin so (150 mil) ds1803 16-pin dip (300 mil) see mech. drawings section on website
ds1803 2 of 11 device operation the ds1803 is an addressable, digi tally controlled device which ha s two 256-position potentiometers. a functional block diagram of the part is shown in figure 1. communicati on and control of the device is accomplished via a 2-wire serial interface. addre ss inputs a0, a1, and a2 allow up to 8 ds1803s to share the same 2-wire interface. each potentiometer is com posed of a 256 position resistor array. two 8-bit registers, ea ch assigned to a respective potentiometer, are used to set the wiper position on the resistor array. the wiper terminal is multiplexed to one of 256 positions on the resistor a rray based on its corresponding 8-bit register value. for example, the high-end terminals, h0 and h1, have wiper position values ffh while the low-end terminals, l0 and l1, have wiper position values 00h. the ds1803 is a volatile device th at does not maintain the position of the wiper during power-down or loss of power. on power-up, the ds1803 wipers? posit ion will be set to position 00h - the low-end terminals. the user may then set the wiper value to a desired position. communication with the ds1803 takes place over the 2-wire serial interface consisting of the bi- directional pin, sda, and the serial clock input, sc l. complete details of the 2-wire interface are discussed in the section entitle d ?2-wire serial data bus.? application considerations the ds1803 is offered in three standa rd resistor values, which include 10k , 50k , and 100k . the resolution of the potentiom eter is defined as r tot /255, where r tot is the total resistor value of the potentiometer. the ds1803 is designed to operate using 3v or 5v power s upplies over the industrial (-40 c to +85 c) temperature range. maximum input signa l levels across the potentiometer cannot exceed the operating power supply of the device. 2-wire serial data bus the ds1803 supports a bi-directional 2- wire bus and data transmission pr otocol. a device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. the device that controls the message is called a ?master?. the devices that ar e controlled by the master are ?slaves?. the bus must be controlled by a master device which generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. the ds1803 operates as a slave on the 2-wire bus. connections to the bus are made via the open-drain i/o lines sda and scl. the following bus protocol has been defined (see figure 2). ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stab le whenever the clock li ne is high. changes in the data line while the clock line is high will be interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line , from high to low, while the clock is high, defines a start condition.
ds1803 3 of 11 stop data transfer: a change in the state of the data line, from low to high, while the clock line is high, defines the stop condition. data valid: the state of the data line represents valid da ta when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. figure 2 details how data transfer is accomplish ed on the 2-wire bus. depe nding upon the state of the r/ w * bit, two types of data transfer are possible. each data transfer is initiated with a start c ondition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is not limited, and is determined by the master device. the information is transferre d byte-wise and each rece iver acknowledges with a ninth bit. acknowledge: each receiving device, when addressed, is ob liged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. a device that acknowledges must pull down the sda lin e during the acknowledge cl ock pulse in such a way that the sda line is stable low during the hi gh period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must si gnal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enab le the master to gene rate the stop condition. 1. data transfer from a master tr ansmitter to a slave receiver: the first byte transmitted by the master is the control byte (slave address). next follows a number of data bytes. the slave returns an acknowledge bit after ea ch received byte. 2. data transfer from a slave tr ansmitter to a master receiver: the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. next follows a number of data bytes transmitted by the slave to the master. the ma ster returns an acknowledge bit after all received bytes other than the last byte. at the end of the la st received byte, a ?not acknowledge? is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next se rial transfer, the bus will not be released. the ds1803 may operate in the following two modes: 1. slave receiver mode: serial data and clock ar e received through sda and sc l. after each byte is received, an acknowledge bit is transmitted. star t and stop conditions are recognized as the beginning and end of a serial tran sfer. address recognition is perfor med by hardware after reception of the slave address and direction bit. 2. slave transmitter mode: the first byte is received and handled as in th e slave receiver mode. however, in this mode the direction bit will indicate th at the transfer direction is reversed. serial data is transmitted on sda by the ds1803 while the seri al clock is input on scl. start and stop conditions are recognized as the begi nning and end of a serial transfer.
ds1803 4 of 11 slave address the control byte is the first byte received followi ng the start condition from the master device. the control byte consists of a four bit control code; for the ds1803, this is 0101 binary. the next three bits of the control byte are the device select bits (a2, a1, a0). they are used by the master device to select which of the devices on the bus are to be accessed. the last bit of the control byte (r/ w *) defines the operation to be performed. when set to a one a read operation is selected, and when set to a zero a write operation is selected. figure 3 s hows the control byte for the ds1803. following the start condition, the ds1803 monitors the sda bus for the control byte being transmitted. upon receiving a matching control byte , the ds1803 outputs an acknowledge signal on the sda line. command and protocol the command and protocol structure of the ds1803 allows the user to read or write the potentiometer(s). the command structures for the part are presented in figures 4 and 5. data is transmitted most significant bit (msb) first. during communication, the recei ving unit always generates the acknowledge. reading the ds1803 as shown in figure 4, the ds1803 provides one read command operation. this ope ration allows the user to read both potentiometer s. specifically, the r/ w bit of the control byte is set equal to a 1 for a read operation. communication to read the ds1803 begins with a start condition which is issued by the master device. the control byte from the mast er device will follow the start condition. once the control byte has been received by the ds1803, the part will respond with an acknowledge. the r/ w bit of the control byte as stated should be set equal to ?1 ? for reading the ds1803. when the master has received th e acknowledge from the ds1803, th e master can then begin to receive potentiometer wiper data. the value of th e potentiometer-0 wiper position will be the first returned from the ds1803. once the eight bits of th e potentiometer-0 wiper position has been transmitted, the master will need to issue an acknowledge, unless it is the only byte to be read, in which case the master issues a not acknowledge . if desired the master may stop the communication transfer at this point by issuing the stop condition. however, if the value of the potentiometer-1 wiper position value is needed, communication transfer can conti nue by clocking the remaining eight bits of the potentiometer-1 value, followed by an not ac knowledge. final communication transfer is terminated by issuing the stop command. writing the ds1803 a data flow diagram for writing the ds1803 is shown in figure 5. the ds1803 has three write commands. these include write pot-0, write pot-1, a nd write pot-0/1. the write pot-0 command allows the user to write the value of pot entiometer-0 and as an option the value of potentiometer-1. the write-1 command allows the user to write the value of pote ntiometer-1 only. the last write command, write-0/1, allows the user to write both potentiometers to th e same value with one command and one data value being issued. all the write operations begin w ith a start condition. following the start condition, the master device will issue the control byte. the read/write bit of the control byte will be set to ?0? for writing the ds1803. once the control byte has been issued and the master receives the acknowledgment from the ds1803, the command byte is transmitted to the ds1803. as mentioned above, there exist three write
ds1803 5 of 11 operations that can be used with the ds1803. the bina ry value of each write command is shown in figure 5 and also in the table 1. 2-wire command words table 1 command command value write potentiometer-0 101010 01 write potentiometer-1 101010 10 write both potentiometers 101011 11
ds1803 6 of 11 absolute maxi mum ratings* voltage on any pin relative to ground -1.0v to +7.0v operating temperature -40 to +85c; industrial storage temperature -55c to +125c soldering temperature 260c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation s ections of this specification is not implied. exposure to absolute maximum rating conditions for extended pe riods of time may affect reliability. recommended operating conditions (-40 c to +85 c) parameter symbol min typ max units notes supply voltage v cc +2.7 5.5 v 1 resistors inputs l,h,w gnd-0.5 v cc +0.5 v 1 dc electrical conditions (-40 c to +85 c; v cc =2.7v to 5.5v) parameter symbol condition min typ max units notes supply current (active) i cc 200 a 3 input leakage i li -1 +1 a wiper resistance r w 400 1000 ohms wiper current i w 1 ma input logic 1 v ih 0.7v cc v cc +0.5 v 2 input logic 0 v il -0.5 0.3v cc v 2 input logic levels a0, a1, a2 input logic 1 input logic 0 0.7v cc -0.5 v cc +0.5 0.3v cc v 12 input current each i/o pin 0.4 ds1803 7 of 11 analog resistor characteristics (-40 c to +85 c;v cc =2.7v to 5.5v) parameter symbol min typ max units notes end-to-end resistor tolerance -20 +20 % 17 absolute linearity 0.75 lsb 13 relative linearity 0.3 lsb 14 -3 db cutoff frequency f cutoff hz 11 temperature coefficient 750 ppm/ c capacitance c i 5 pf ac electrical characteristics (-40 c to +85 c;v cc =2.7v to 5.5v) parameter symbol min typ max units notes scl clock frequency f scl 0 0 400 100 khz 15 16 bus free time between stop and start condition t buf 1.3 4.7 s 15 16 hold time (repeated) start condition t hd:sta 0.6 4.0 s 5 low period of scl clock t low 1.3 4.7 s high period of scl clock t high 0.6 4.0 s data hold time t hd :dat 0 0 0.9 s 6,7 data setup time t su :dat 100 250 ns 8 rise time of both sda and scl signals t r 20+1c b 300 1000 ns 9 fall time of both sda and scl signals t f 20+1c b 300 300 ns 9 setup time for stop condition t su:sto 0.6 4.0 s capacitive load for each bus line c b 400 pf 9 notes: 1. all voltages are referenced to groun d. currents flowing into device pi ns are positive. currents out of the device pins are negative. 2. i/o pins of fast mode devices will not obstruct sda and scl even if v cc is switched off. 3. i cc specified with sda pin open, scl = 400 khz clock rate. 4. i stby specified with v cc at 5.0v and sda, scl = 5.0v.
ds1803 8 of 11 5. after this period, the first clock pulse is generated. 6. a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) in order to bridge the undefined region of the falling edge of scl. 7. the maximum t hd:dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. 8. a fast mode device can be used in a standard mode system, but the requirement t su:dat > 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su:dat = 1000 + 250=1250 ns before the scl line is released. 9. c b - total capacitance of one bus line in picofarads, timing referenced to (0.9)(v cc ) and (0.1)(v cc ). 10. typical values are for t a = 25 c and nominal supply voltage. 11. -3 db cutoff frequency characteristics for th e ds1803 depend on potentiometer total resistance: ds1803-010; 1 mhz, ds1803-50; 200 khz, ds1803-100; 100 khz. 12. address inputs, a0, a1, and a2, should be tied to either v cc or gnd depending on the desired address selections. 13. absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper position. device test limits are 1.6 lsb. 14. relative linearity is used to determine the change in voltage between successive tap positions. device test limits 0.5 lsb. 15. fast mode. 16. standard mode. 17. valid at 25 c only.
ds1803 9 of 11 ds1803 block diagram figure 1 2?wire data transfer overview figure 2
ds1803 10 of 11 control byte figure 3 2?wire read protocol figure 4 2?wire write protocol figure 5 write pot-0
ds1803 11 of 11 timing diagram figure 6 ds1803 ordering information ordering number package operating temperature version ds18030-010 16l dip -40c to +85c 10 k ? ds18030-050 16l dip -40c to +85c 50 k ? ds18030-100 16l dip -40c to +85c 100 k ? ds1803e-010 14l tssop (173 mil) -40c to +85c 10 k ? ds1803e-050 14l tssop (173 mil) -40c to +85c 50 k ? ds1803e-100 14l tssop (173 mil) -40c to +85c 100 k ? ds1803z-010 16l soic (150 mil) -40c to +85c 10 k ? ds1803z-050 16l soic (150 mil) -40c to +85c 50 k ? ds1803z-100 16l soic (150 mil) -40c to +85c 100 k ? ds1803e-010+ 14l tssop (173 mil) lead free -40c to +85c 10 k ? ds1803e-50+ 14l tssop (173 mil) lead free -40c to +85c 50 k ? ds1803e-100+ 14l tssop (173 mil) lead free -40c to +85c 100 k ? ds1803e-010+t&r 14l tssop (173 mil) lead free t&r -40c to +85c 10 k ? ds1803e-50+t&r 14l tssop (173 mil) lead free t&r -40c to +85c 50 k ? ds1803z-010+ 16l soic (150 mil) lead free -40c to +85c 10 k ? ds1803z-050+ 16l soic (150 mil) lead free -40c to +85c 50 k ? ds1803z-100+ 16l soic (150 mil) lead free -40c to +85c 100 k ? ds1803z-010+t&r 16l soic (150 mil) lead free t&r -40c to +85c 10 k ? ds1803z-050+t&r 16l soic (150 mil) lead free t&r -40c to +85c 50 k ? ds1803z-100+t&r 16l soic (150 mil) lead free t&r -40c to +85c 100 k ? ds1803-100+t&r 16l dip t&r -40c to +85c 100 k ? ds1803e-10/t&r 14l tssop (173 mi l) t&r -40c to +85c 10 k ? ds1803e-50/t&r 14l tssop (173 mi l) t&r -40c to +85c 50 k ? ds1803e-100/t&r 14l tssop (173 mi l) t&r -40c to +85c 100 k ? ds1803z-010/t&r 16l soic (150 mil) t&r -40c to +85c 10 k ? ds1803z-050/t&r 16l soic (150 mil) t&r -40c to +85c 50 k ? ds1803z-100/t&r 16l soic (150 mil) t&r -40c to +85c 100 k ?
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